1. Technical Field
The present invention relates to a method and system for integrated circuit design in general and, in particular, to an automated method and system for integrated circuit design. Still more particularly, the present invention relates to an automated method and system for performing timing analysis on an integrated circuit design.
2. Description of the Prior Art
Logic synthesis has now become an integral part of an integrated circuit (IC) design automation process. A logic synthesis system typically contains various analysis programs (or analysis tools), each intended for achieving a different purpose, such as logic design, circuit area targeting, timing and delay analysis, etc. These analysis programs play an important role in the design automation process, both in their own right as well as part of a logic synthesis system that utilizes them to evaluate the quality of various synthesized circuits extracted from the IC design.
Generally speaking, a timing analysis program analyzes the temporal behavior of an IC design by determining when a timing event occurs within the IC design. For example, in a synchronized digital system design, the timing analysis program is utilized to determine the delay of a combinational part of an IC design. The delay of the combinational circuit is the time taken for the outputs of the combinational circuit to settle at a final value after the inputs have been applied. This delay, in turn, is utilized to determined the minimal permissible clocking period of the entire digital system design.
Before timing analysis is performed, RC delays and capacitance on an IC design are calculated on a per net basis by an IC design extraction program. The results from such calculation are then fed into a timing analysis program such that various cycle times of the IC design can be determined. One problem with the prior art timing analysis programs is that they typically take an extensive amount of time to generate a complete set of physical data for the entire IC design. Thus, most circuit designers often defer the full-cycle of creating the complete set of physical data in order to gain extra design time. Even though such a solution may be acceptable at times, it is always advantageous to be able to conveniently perform a timing analysis on the entire IC design in order to gain more accurate timing information about the design at any stage of the design process. Hence, it would be desirable to provide an improved method and system for performing timing analysis on an IC design in order to facilitate the IC design automation process.